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Computer Architecture:  2017-2018

Lecturer

Degrees

Schedule S1(CS&P)Computer Science and Philosophy

Schedule B1 (CS&P)Computer Science and Philosophy

Schedule S1Computer Science

Schedule B1Computer Science

Schedule S1(M&CS)Mathematics and Computer Science

Schedule B1Mathematics and Computer Science

Term

Overview

This course aims to give an understanding of the mechanisms for implementing the programmer's idealised computer. It builds on the introduction to hardware and to simple processors in the Digital Systems course. The Computer Architecture course aims to describe a broad range of architectural designs and to contrast them, highlighting the design decisions they incorporate, and how these design decisions impact program performance. 

Practicals

x86/Y86 assembler, pipelined processors, out-of-order execution and program performance, GPGPU programming

Learning outcomes

By the end of the course, the student should understand the major architectural styles and appreciate the compromises that they encapsulate. They should be able to read outline descriptions of real processors and understand in which way their designs fit into the frameworks described in the course. They should also be able to understand the impact of design choices in programming in the context of a specific architecture.

Prerequisites

Students who have not taken Digital Systems will need to do additional background reading on combinational circuts and assembler programming.

Synopsis

  1. Introduction and overview
  2. C programming language
  3. x86-64 assembly language
  4. Machine representation of programs
  5. Control structures for processors, register transfer level description of hardware
  6. Hardware description languages and simulation in Verilog
  7. Instruction set design, instruction formats, addressing modes, ISAs
  8. A sequential Y86-64 design
  9. Processor pipelining, pipeline hazard detection, stalling and forwarding
  10. Out-of-order execution and program performance optimisation
  11. RISC and CISC instruction sets (MIPS, ARMv8 and x86-64)
  12. Vector operations and single-instruction multiple-data (SIMD) operations
  13. General purpose graphics processing unit computing (GPGPU) and OpenCL  
  14. Memory hierachy and memory caches
  15. Micro-controllers for embedded applications
  16. Alternative architectures - stack and accumulator machines

Syllabus

C programming language; x86-64 assembly language; Machine representation of programs; Control structures for processors, register transfer level description of hardware; Hardware description languages and simulation in Verilog; Instruction set design, instruction formats, addressing modes, ISAs; A sequential Y86-64 design; Processor pipelining, pipeline hazard detection, stalling and forwarding; Out-of-order execution and program performance optimisation; RISC and CISC instruction sets (x86-64 and ARMv8); Vector operations, SIMD and GPGPU; Memory hierachy and memory caches; Micro-controllers for embedded applications; Alternative architectures.

Reading list

The principal text is:

  • R E Bryant & D R O'Hallaron, Computer Systems: A Programmer's Perspective, Pearson (Global edition) 2015.

The following text is recommended but focuses more on the MIPS architecture:

  • D A Patterson & J L Hennessy, Computer Organization and Design: The hardware/software interface, Morgan-Kaufmann (Fifth edition) 2013.

Additional background reading will be identified throughout the course.