Yuguang Huang, Date to be advised, 25pp
Abstract:
In this paper, a BSP (Bulk Synchronous Parallel) Bareiss algorithm for Toeplitz system is proposed. We investigate various data distribution and scheduling strategies for mapping of a typical class of systolic array algorithms onto the BSP machines. Load balance both in communication and computation as well as linear speedup have been achieved for the Toeplitz system solver and at the same time minimum memory requirement is reserved. The code is compiled and tested on the Sun workstations, SGI Power Challenge and IBM SP2 parallel machines using the Oxford BSPlib [23].
Keywords: Bulk Synchronous Parallel, Bareiss algorithm, Toeplitz system, Parallel algorithm.