Towards the Formal Verification of Lower System Layers in Automotive Systems
Sven Beyer‚ Peter Böhm‚ Michael Gerke‚ Mark Hillebrand‚ Thomas In der Rieden‚ Steffen Knapp‚ Dirk Leinenbach and Wolfgang J. Paul
The mission of the Verisoft project is (i) to develop techniques, which permit the pervasive formal verification of computer systems comprising hardware, system software, communication systems, and applications, (ii) to apply these techniques in an industrial context to verify prototypical systems. One such application is an emergency call, which is automatically placed on the mobile phone net after the sensors of a car have detected that it was involved in a crash. The application runs on a system of several electronic control units (ECUs). The local application programs of the ECUs run on top of a simple real time operating system kernel like described in the OSEKTime standard. ECUs are connected via a FlexRay bus. We outline the structure of an overall correctness proof for such a parallel system from the gate to the kernel level. For the communication system hardware one has to combine existing correctness proofs for components of time triggered architectures (e.g. clock synchronization) and arguments about hardware correctness into a single theorem. Results on processor, driver, and kernel correctness can to a large extent be imported from existing research in the Verisoft project. Worst case execution time bounds are derived with advanced industrial tools based on abstract interpretation.
23rd International Conference on Computer Design (ICCD '05)
IEEE Computer Society