Test set generation and fault localization software for reversible circuits
Dean Pierce‚ Jacob Biamonte and Marek Perkowski
Abstract
We discuss some properties of reversible circuits that allow them to be tested more efficiently than their classical counterparts, and give an analysis of currently proposed fault models. We also present an efficient algorithm that can be used to generate fault localization trees for large circuits.
How Published
Proceedings
Journal
Proc. 7th International Symposium on Representations and Methodologies for Emergent Computing Technologies‚ Tokyo‚ Japan
Keywords
Reversible circuits‚ test‚ design for test‚ verification
Month
Sep
Pages
8
Year
2005