Computer Architecture: 2013-2014
This course aims to give an understanding of the mechanisms for implementing the programmer's idealised computer. It builds on the introduction to hardware and to simple processors in the Digital Systems course. The Computer Architecture course aims to describe a broad range of architectural designs and to contrast them, highlighting the design decisions they incorporate. The designs are described and analysed at the register-transfer level of abstraction. The course has an emphasis on understanding concurrency and power implications of design choices.
x86/Y86 assembler, multi-core concurrency, GPGPU programming
Learning outcomesBy the end of the course, the student should understand the major architectural styles and appreciate the compromises that they encapsulate. They should be able to read outline descriptions of real processors and understand in which way their designs fit into the frameworks described in the course. They should also be able to understand the impact of design choices in programming in the context of a specific architecture.
Students who have not taken Digital Systems will need to do additional background reading on combinational circuts and assembler programming.
- Introduction and overview
- Datapaths and control structures for processors, register transfer level description of hardware
- Design and Simulation in Verilog and C++/SystemC
- Instruction set design, instruction formats, addressing modes, ISAs
- A simple, MIPS-based RISC design
- A simple x86 (CISC) design, microcode
- Processor pipelining, pipeline hazards
- Hazard detection, forwarding
- Branch prediction and other kinds of speculation
- Out-of-order execution and register renaming
- Reorder buffers
- GPGPU designs
- Main and cache memories
- Multi-cores and cache coherency, weak memory consistency
- Architectures without shared memory
SyllabusRegister Transfer model of processors. Datapaths and control structures. Comparison of architectural styles for general purpose computers, including RISC/CISC. Pipelining; pipeline hazards and their resolution by stalling and forwarding. Techniques for executing more than one instruction in each clock cycle. The hierarchy of storage in a computer; caches and virtual memory. Styles of parallel computers, and their implementation in contemporary designs.
Principal texts; either one of:
- D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Fourth edition) 2009.
- D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Third edition, revised printing) 2007.
The fourth edition covers more recent designs and is preferred; the third edition still covers multi-cycle designs, which
are no longer relevant. Either one should be adequate, if available. Similarly, the second edition is relevant if available,
but may be confusing.
- Some articles (to be identified near the time of the course) about contemporary designs.
- K. Stevens et al., An Asynchronous Instruction Length Decoder
- R.M. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units