Embedded Handel for Hardware Design
Supervisor
Suitable for
Abstract
HANDEL (designed in this Department by the hardware compilation group led by Ian Page) was one of the very earliest serious attempts to demonstrate that
Hardware should be described by a programming language, not as wires and registers.
The key ideas of Handel were rooted in: strong static typing, concurrency as a first-class concept, and its semantics were rooted in csp / occam. For comparison with a somewhat lower-level language in which concurrency is implicit, see [4].
In its prototype implementation it was embedded (in a niche-programming language: Standard ML). Its successful application to designs that were to be implemented using (then nascent) Field Programmable Gate Array technology[1,2] led to a successor language, Handel-C[3], being built commercially, and adopted as a hardware design tool of choice within the academic community, especially in the United Kingdom. The demise of Handel-C has been authoritatively attributed to the very high cost and proprietary nature of parts of its toolchain.
These days FPGAs are available at a variety of scales, for example (high end) AMD/Xilinx "Virtex" Ultrascale with ~9 million logic cells, costing tens of thousands of pounds per chip and (low end) Lattice CE40UP5K with up to ~5,000 cells with typical board costs of a few tens of pounds. Lattice is well supported by open toolchains. The time is ripe for reviving Handel.
The goal of this project is to embed an implementation of Handel in Scala, generating output for synthesis by an open-source tool-chain.
References:
- https://www.cs.ox.ac.uk/people/bersufrin/personal/HANDEL/pproc.pdf - PARAMETRISED PROCESSOR GENERATION
- https://www.cs.ox.ac.uk/people/bernard.sufrin/personal/HANDEL/wotug94v - Automatic Design and Implementation of Microprocessors
- https://en.wikipedia.org/wiki/Handel-C - HANDEL-C
- https://www.cs.ox.ac.uk/people/bernard.sufrin/personal/HANDEL/Operation-centric_hardware_description_and_synthesis.pdf