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Modelling and verifying systems in Timed CSP and FDR

Supervisor

Suitable for

MSc in Computer Science
Mathematics and Computer Science, Part C
Computer Science, Part C
Computer Science, Part B 2017-18

Abstract

Timed CSP reinterprets the CSP language in a real-time setting and has a semantics in which the exact times of events are recorded as well as their order. Originally devised in the 1980s, it has only just been implemented as an alternative mode for FDR. The objective of this project is to take one or more examples of timed concurrent system from the literature, implement them in Timed CSP, and where possible compare the performance of these models with similar examples running on other analysis tools such as Uppaal.

References:

(Reference Understanding Concurrent Systems, especially Chapter 15, and Model Checking Timed CSP, from AWR's web list of publications)