ATPG for reversible circuits using technology−related fault models

Abstract

We address the problem of test set generation and test set reduction, to first detect, and later localize faults occurring in reversible circuits. Reversible Computation has high promise of low power consumption. Some new fault models are first presented here. An explanation of the new fault models is made based on a physical realization representing the state of the art in the reversible CMOS circuit technology. Evidence is then presented showing that the fault models presented in the current literature are not adequate for existing realizations of reversible logic such as CMOS. We designed a ATPG software package with a friendly graphical user interface to aid experimentation with various fault models. The purpose of this work is to give an overview of our findings and pave the way for a later paper fully addressing the CMOS fault models. The key experimental results are presented.