Skip to main content

Parallelising Compiler for Green Multicore Computing

Professor Hironori Kasahara ( Waseda University )

High performance and low power, or green, computing is essential for various ICT products from smartphones, self-driving vehicles, cancer treatment systems to cloud and High-Performance servers. To realise these systems, a low-power, high performance, and user-friendly multicore and its compiler are key technologies. This talk introduces "OSCAR (Optimally Scheduled Advanced Multiprocessor)" multicore compiler, which has been researched for 35 years in Waseda University, based on "green multigrain parallelisation" based on coarse-grain task parallelization and loop parallelisation, global data locality optimization, automatic power reduction control using DVFS, clock and power gating, software cache coherent control, and automatic local memory management for hard real-time control applications. Performance and power evaluation on various multicores, such as Intel, ARM, IBM, Fujitsu, Renesas, Infineon, and RISC V, are also shown in the talk.


Professor Hironori Kasahara is IEEE Computer Society (CS) President 2018 and a senior executive vice president of Waseda University, Tokyo, Japan. He received BS in 1980, MSEE in 1982, PhD in 1985 from Waseda University, joined its faculty in 1986 and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at the University of California, Berkeley, in 1985 and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D from 1989 to 1990. Dr. Kasahara received IEEE Fellow in 2017, CS Golden Core Member Award (2010), IEEE Eta Kappa Nu Professional Member (2017), IFAC World Congress Young Author Prize (1987), IPSJ (Information Processing Society of Japan) Sakai Special Research Award (1997), IPSJFellow (2015), Member of the Engineering Academy of Japan (2017), Member of the Science Council of Japan (2017) and a Science and Technology Prize of the Japanese Minister of Education, Culture, Sports, Science and Technology in 2014. He led Japanese national projects supported by METI (Ministry of Economy, Trade and Industry of Japan)/NEDO on parallelising compilers, embedded multicores for consumer electronics, and Green Computing. He has presented 216 papers, 180 invited talks, and 48 international patents. His research on multicore architectures and software has appeared in 612 newspaper and Web articles. He has served as chair or member of 260 society and government committees; such as CS Board of Governors, Executive Committee, Planning Committee, chair of CS Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers, vice PC chair of the 1996 ENIAC 50th Anniversary ACM International Conference on Supercomputing, general chair of LCPC 2012, PC member of SC, PACT, and ASPLOS, board member of IEEE Tokyo Section, and member of the MEXT(Ministry of Education, Culture, Sport, Science and Technology of Japan) Earth Simulator Supercomputer committee and Information Science and Technology Committee.




Share this: