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Compiling SPICE to an FPGA - A Retrospective

Nachiket Kapre

Info

Date

23rd November 2011 (week 7, Michaelmas Term 2011)

Time

11:30

Place

147

Abstract

Spatial processing of the SPICE circuit simulator using reconfigurable architectures (i.e. FPGAs) can deliver an order of magnitude speedup over conventional processors (i.e. Intel multi-core CPUs) for a range of benchmark circuits. SPICE has historically been hard to parallelize due to the irregular nature of the computation. In this talk, I show how to expose the different, irregular parallel patterns inherent in SPICE using a high-level, domain-specific framework capable of composing multiple patterns simultaneously on the same FPGA fabric. I will also briefly overview some recent, preliminary enhancements that can further improve the SPICE FPGA design.

Speaker bio

Nachiket Kapre is currently a Junior Research Fellow at Imperial College London. He received his PhD (2010) and M.S (2005-EE, 2006-CS) from California Institute of Technology, USA. His thesis shows how to effectively implement the SPICE circuit simulator using fine-grained, spatial FPGA logic through a domain-specific compilation flow and an application-specific compute organization. He is primarily interested in understanding and exploiting the potential of spatial parallelism for implementing computation. His broader research interests include parallel processing, high-level system architectures and domain-specific programming frameworks.

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