Dr Ziyad Hanna
Research and Development Interest:
- Formal Specification and Verification
- Model Checking, deductive reasoning, SAT, SMT, BDDs
- Formal Equivalence Checking and design signoff
- Verification IP for standard interfaces, memory IPs and on-chip connectivity
- Machine Learning, Artificial Intelligence and optimization
- Software verification and static analysis
- System design and functional validation flows and methodologies
- Computer architecture and modeling
- Logic synthesis and chip design implementation
- Safety and security of software and hardware systems
- Quantum Computing
- Computation logistics and big data
- Automatic root-cause analysis and debugging techniques
- Bug localization with Machine Learning
- Management and leadership of multinational R&D center of expertise
Ziyad Hanna, PhD. in computer science from the university of Oxford and has more than 30 years of industrial experience earned during his tenure in several international and leading companies including Intel, Jasper Design Automation and Cadence Design Systems. Today Ziyad is a Corporate Vice President of Cadence Design Systems, Fellow, and the R&D General Manager of Cadence Israel, leading the company’s technology innovations and business in Electronic Design Automation domains with focus on software and hardware verification technologies and solutions for the fast-emerging worldwide chip design industry.
During his career Ziyad’s major focus has been on advancing the breakthroughs in functional design and formal verification technology for software and hardware systems, including core model checking and reachability algorithms, static analysis, system architecture and verification solutions in all areas of front-end design and verification, including architectural modeling, protocols and verification IP, chip design and verification modeling, security and safety verification, constraints solving, automatic test generation, verification management systems, machine learning, System-on-Chip design and verification, debugging and root-cause-analysis technologies, computational logistics for higher verification throughput, post-silicon bring up and many more. In his current position at Cadence Design Systems, Ziyad is leading 10 R&D centers in different countries, where it has the largest and most advanced industrial formal verification research and development group worldwide. Ziyad chairs the annual Jasper User Group (JUG) conference, the largest industrial formal verification event which has being running annually for that last 14 years and attracting thousands of technology leaders and experts from both academia and industry worldwide.
Prior to Cadence, Ziyad was the Jasper’s senior Vice President and General Manager of Jasper Israel the first startup company that made its way to company exit in Formal Verification domain. At Jasper, Ziyad was the chief scientist, R&D senior vice president and architect of the JasperGold formal verification platform and applications, which made the breakthrough in applying formal verification methods for the worldwide chip design industry. Jasper won the Red Herring award for being the “Top 100 North America Company” in 2013. Jasper conquered the formal verification domain to reach the valuable acquisition in June/2014 by Cadence Design Systems.
Before joining Jasper, Ziyad was Intel senior principal engineer (Sr. PE) and the leader (GL) of the Formal Technology Research and Development Group in the Design and Technology division at Intel Haifa. While at Intel, Ziyad was instrumental in the development of several generations of formal verification systems used on almost all Intel microprocessor designs since early 1990s.
A senior IEEE member, Ziyad has been active in formal verification domain for over 30 years and has mentored many research projects with academia and served in various international conferences including FMCAD, SAT, ICCAD, DAC, HVC, and ICCD. He has published more than 45 papers and articles mainly in the formal verification area, holds 15 patents, several at pending state, and gave hundreds of talks in numerous domestic and international conferences. He received both his B.Sc. and M.S. degrees in math and computer science at Tel-Aviv University, and PhD. (DPHIL) in computer science, and his thesis was on “A Symbolic Execution Framework for Algorithmic-Level Modelling and Verification of Computer Microarchitecture” from the Oxford University - England. Ziyad is a visiting professor in the computer science department at Oxford university representing Cadence or driving the research agenda in logic reasoning, machine learning for the emerging software and hardware design and verification systems. Ziyad served on program committees for international conference, gave talks and delivered courses and mentored research in his area with leading edge professors from US, Europe, and Israeli universities. Ziyad received numerous prestigious awards including Intel's highest achievement award (IAA) twice, Jasper Red Herring award, Cadence move-the-needle award and many more.
Ziyad has been highly involved in his society, severing in the association for advancing the higher education in the Arab community in Israel, co-chainring the Israeli public Hi-Tech Council, was a member of a start up team for building the international campus of the Indianapolis University in the north of Israel, where he served the head of computer science department. Ziyad is very active in promoting and advising for several startup companies in Israel. He won the Israeli presidential award because of his active volunteering in his community and was ranked number 39 in TheMarker’s 100 most influential people on the Israel life for year 2019, also top the list in the Hi-Tech category. Ziyadname was listed in the most influential people in Hi-Tech for 2020 in Israel by “People and Computers” magazine.Since July/2019 he co-led the 5-years planning initiative to advance the Hi-Tech in the Arab community in Israel which received the Israeli endorsement and funding through 2026.
- System Verification Group