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Ziyad Hanna

Personal photo - Ziyad Hanna

Ziyad Hanna

Doctoral Student


Ziyad Hanna is currently a Vice President and Chief Architect at Jasper Design Automation. He is responsible for advancing the company’s breakthroughs in formal verification technology and applications. Prior to joining Jasper, Ziyad was Intel senior principal engineer and the leader of the Formal Technology Research and Development Group in the Design and Technology Solutions division at Intel Haifa. While at Intel, Ziyad was instrumental in the development of several generations of formal verification systems used on almost all Intel microprocessor designs since early 1990s. A senior IEEE member, Ziyad has been active in the area of formal verification for over 20 years, and has mentored many research projects with academia and served in various international conferences including SAT, ICCAD, DAC, CAV, MBT, FMCAD, ICCD and more. He has published more than 25 articles the formal area and holds 8 patents. He received both his B.Sc. and M.S. degrees in computer science at Tel-Aviv University, and is working towards his Ph.D. with research in “Abstract Modeling and Formal Verification of Microprocessors” at the Department of Computer Science, University of Oxford