Compiling SPICE to an FPGA - A Retrospective
- 11:30 23rd November 2011 ( week 7, Michaelmas Term 2011 )147
Spatial processing of the SPICE circuit simulator using reconfigurable architectures (i.e. FPGAs) can deliver an order of magnitude speedup over conventional processors (i.e. Intel multi-core CPUs) for a range of benchmark circuits. SPICE has historically been hard to parallelize due to the irregular nature of the computation. In this talk, I show how to expose the different, irregular parallel patterns inherent in SPICE using a high-level, domain-specific framework capable of composing multiple patterns simultaneously on the same FPGA fabric. I will also briefly overview some recent, preliminary enhancements that can further improve the SPICE FPGA design.