Domain-Specific Programming of Very High Speed Packet Processing
Programmable logic has been in the peripheral vision of computer science for the past 25 years or so. While the idea of ‘soft hardware’ has seemed full of potential, productive application has been held back by two main factors: the small size of the physical devices, and the programming experience being akin to hardware chip design. The former issue has now been ameliorated by the emergence of modern FPGA devices containing millions of programmable logic gates, plus other embedded processing and memory. The latter issue is the subject of this talk. One line of attack is attempting to map general-purpose programming languages, with “automatic extraction of parallelism”. I prefer a domain-specific approach, looking to map natural domain parallelism onto the fine-grain concurrency of the FPGA. The talk will focus on the particular domain of packet processing. It has been shown that FPGAs have the raw capability to perform packet processing at very high data rates, currently up to 100-200 Gb/s, with 400 Gb/s and 1Tb/s on the horizon. The challenge is to allow the networking programmer in the street to describe packet processing problem instances, and automatically obtain FPGA solutions that deliver the required performance with acceptable power consumption. I will describe research on domain-specific languages for packet processing that has gone through several generations since 2005. Recent work demonstrated high-level packet parsing descriptions being compiled into 400 Gb/s rate FPGA implementations. The story of this research will not just cover the technicalities, but will also include discussion of what directions proved acceptable to the target audience, and what did not.