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Computer Architecture:  2014-2015



Schedule S1Computer Science

Schedule B1Computer Science

Schedule B1Mathematics and Computer Science



This course aims to give an understanding of the mechanisms for implementing the programmer's idealised computer. It builds on the introduction to hardware and to simple processors in the Digital Systems course. The Computer Architecture course aims to describe a broad range of architectural designs and to contrast them, highlighting the design decisions they incorporate. The designs are described and analysed at the register-transfer level of abstraction. The course has an emphasis on understanding concurrency and power implications of design choices.


x86/Y86 assembler, multi-core concurrency, GPGPU programming

Learning outcomes

By the end of the course, the student should understand the major architectural styles and appreciate the compromises that they encapsulate. They should be able to read outline descriptions of real processors and understand in which way their designs fit into the frameworks described in the course. They should also be able to understand the impact of design choices in programming in the context of a specific architecture.


Students who have not taken Digital Systems will need to do additional background reading on combinational circuts and assembler programming.


  1. Introduction and overview
  2. Datapaths and control structures for processors, register transfer level description of hardware
  3. Design and Simulation in Verilog and C++/SystemC
  4. Instruction set design, instruction formats, addressing modes, ISAs
  5. A simple, ARM-based RISC design
  6. A simple x86 (CISC) design, microcode
  7. Processor pipelining, pipeline hazards
  8. Hazard detection, forwarding
  9. Branch prediction and other kinds of speculation
  10. Out-of-order execution and register renaming
  11. Reorder buffers
  12. GPGPU designs
  13. Main and cache memories
  14. Multi-cores and cache coherency, weak memory consistency
  15. Architectures without shared memory
  16. Revision


Register Transfer model of processors. Datapaths and control structures. Comparison of architectural styles for general purpose computers, including RISC/CISC. Pipelining; pipeline hazards and their resolution by stalling and forwarding. Techniques for executing more than one instruction in each clock cycle. The hierarchy of storage in a computer; caches and virtual memory. Styles of parallel computers, and their implementation in contemporary designs.

Reading list

Principal texts; either one of:

  • D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Fifth edition) 2013.
  • D A Patterson & J L Hennessy, Computer Organization and Design: the hardware/software interface, Morgan-Kaufmann (Fourth edition) 2009.

The fifth edition covers more recent designs and is preferred, but the differences to the fourth edition are marginal. Either one should be adequate. The third edition still covers multi-cycle designs, which are no longer relevant, and may thus be confusing.

Background reading: