Creating an Agile Hardware Design Flow
- 11:00 27th November 2019 ( Michaelmas Term 2019 )Lecture Theatre B, Department of Computer Science, Wolfson Building, Parks Road, Oxford OX1 3QD
Although an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. Stanford's AHA (Agile HArdware) project is working towards this goal while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA), that functions as our hardware accelerator. As our understanding of the application grows, the CGRA design evolves, and we have developed a suite of tools that allow this to happen. We fabricated our first CGRA, called Jade, last year. With that development experience in hand, we have worked on ways to tune the application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our need to continually update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators which not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach to design and evolve high performance and energy-efficient hardware-software systems for any application domain. More details about the Stanford AHA project can be found on our website: https://aha.stanford.edu. All the tools and hardware designed as a part of this project are open-source and can be found on our github page: https://github.com/StanfordAHA.
Bio: Priyanka Raina is an Assistant Professor in Electrical Engineering at Stanford University. Previously, she was a Visiting Research Scientist in the Architecture Research Group at Nvidia Corporation. She received her Ph.D. and S.M. degrees in Electrical Engineering and Computer Science from MIT in 2018 and 2013 and her B.Tech. degree in Electrical Engineering from IIT Delhi in 2011. Priyanka's research interests include designing energy-efficient and high-performance hardware accelerator architectures for computational imaging, vision, and machine learning; leverage emerging device technologies such as non-volatile memories in accelerators, and creating new methodologies and automation tools that improve hardware/software system design productivity. Her website is at https://engineering.stanford.edu/people/priyanka-raina.