Tom Melham

Professor Tom Melham FRSE

Professor of Computer Science

Tutorial Fellow, Balliol College

T: +44 (0)1865 273824

Themes:

• Automated Verification

Completed Projects:

• Model Checking Partially Ordered State Spaces
• more…

See Also:

• Personal Web Pages
• List of all Publications

Selected Publications

View AllManage publications

• Active Learning of Abstract System Models from Traces using Model Checking

  Natasha Yogananda Jeppu‚ Tom Melham and Daniel Kroening

  In Cristiana Bolchini‚ Ingrid Verbauwhede and Ioana Vatajelu, editors, 2022 Design‚ Automation & Test in Europe Conference & Exhibition‚ DATE 2022‚ Antwerp‚ Belgium‚ March 14−23‚ 2022. Pages 100–103. IEEE. March, 2022.

  Details about Active Learning of Abstract System Models from Traces using Model Checking | BibTeX data for Active Learning of Abstract System Models from Traces using Model Checking | DOI (10.23919/DATE54114.2022.9774595) | Download (pdf) of Active Learning of Abstract System Models from Traces using Model Checking

• Active Learning of Abstract System Models from Traces using Model Checking [Extended]

  Natasha Yogananda Jeppu‚ Tom Melham and Daniel Kroening

  In arXiv Computing Research Repository. Vol. arXiv:2112.05990 [cs.FL]. December, 2021.

  Details about Active Learning of Abstract System Models from Traces using Model Checking [Extended] | BibTeX data for Active Learning of Abstract System Models from Traces using Model Checking [Extended] | Link to Active Learning of Abstract System Models from Traces using Model Checking [Extended]

• End−to−End Formal Verification of a RISC−V Processor Extended with Capability Pointers

  Dapeng Gao and Tom Melham

  In Ruzica Piskac and Michael W. Whalen, editors, Proceedings of the 21st Conference on Formal Methods in Computer−Aided Design –− FMCAD 2021. Vol. 2. Pages 24–33. TUI Wien Academic Press. October, 2021.

  Details about End−to−End Formal Verification of a RISC−V Processor Extended with Capability Pointers | BibTeX data for End−to−End Formal Verification of a RISC−V Processor Extended with Capability Pointers | DOI (10.34727/2021/isbn.978-3-85448-046-4_10) | Download (pdf) of End−to−End Formal Verification of a RISC−V Processor Extended with Capability Pointers

Activities

• Hardware Verification

Projects

• Effective Validation of Firmware

Completed Projects

• Model Checking Partially Ordered State Spaces
• Verified Communication Protocols for Multicore/SoC Architectures
• Metacomputation

Current Students

Past Students

Past Researcher